The new multicore architecture features up to three processor cores to share the application load, introduces lockstep cores and contains further enhanced hardware safety mechanisms. A first implementation of the architecture is available to selected customers for architecture exploration and early prototyping.

The new multicore architecture contains up to three TriCore processor cores connected over a crossbar running at the full CPU speed and avoiding hardware contentions. Additionally, the architecture implements multiple program Flash modules with independent read interfaces which further support the real-time capability.

Additional innovations of the new architecture include a new timer module which offloads the CPUs, and new Analog to Digital Converters including Delta Sigma converters with a high accuracy and a high sampling rate.

The 65nm embedded Flash silicon process technology and the microcontroller architecture are designed to balance increased performance with the need for lower power consumption. Additional low power modes are supported to enable very low standby current consumption.

Infineon’s multicore architecture introduces methods to meet the newly introduced ISO 26262 Automotive safety standard. Design, implementation and documentation are focused for compliance to the highest Automotive Safety Integrity Level (ASIL D).

Two of the three TriCore CPUs feature additional Lockstep cores which can be independently configured. Further implemented safety techniques include, for example, safe internal communication buses, a Bus Monitoring Unit, and both error detection code (EDC) and error correction code (ECC) on all memories. A distributed memory protection system operates on core level, bus level and on peripheral level. These enhanced encapsulation techniques allow the integration of software with mixed criticality levels from different sources, allowing hosting of multiple applications and operating systems on a unified platform.

The multicore architecture features a hardware security module (HSM) to meet upcoming security requirements to better protect automotive applications from tampering or potential hacking attacks. The HSM uses leading edge hardware-based security technology developed by Infineon.

The 65nm embedded Flash technology is designed for highest reliability in the harsh automotive environment. End-of-line programming speed of the embedded Flash is up to 20 times faster than in the previous generation of Infineon’s microcontrollers. This is especially important due to the increased amount of embedded Flash required by automotive systems, the company noted.

The first implementation of the multicore architecture, the Development Device, is now available for prototyping to selected customers. Automotive system suppliers can start now to explore the multicore architecture’s features and develop their multicore software implementation. The 65nm Development Device contains three TriCore CPUs, two of them with lockstep implementation, and 4MByte of embedded Flash.

First products of the AURIX family are scheduled to be available by mid 2012, with qualification planned in the second half of 2013.

In 1999, Infineon launched the first generation of AUDO (AUtomotive unifieD processOr), based on a unified RISC/MCU/DSP processor core. Infineon evolved and optimized this 32-bit TriCore microcontroller, resulting in the current, fourth-generation, which is used in the company’s AUDO MAX family.